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[VHDL-FPGA-Verilog] VHDLcodes

Description: Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.
Platform: | Size: 6144 | Author: Vijay | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 包含CPU每部分器件的编写，通过改写RAM内容，可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
Platform: | Size: 2151424 | Author: Sophie | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram configuration module can be directly useful
Platform: | Size: 79872 | Author: 熊文 | Hits:

[VHDL-FPGA-Verilog] RamFifoVHDL

Description: Ram Fifo Core VHDL file
Platform: | Size: 21504 | Author: Marcos Vinícius | Hits:

[Other] dualportram_vhdl

Description: 采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化-VHDL hardware description language using the dual-caliber RAM block memory initialization
Platform: | Size: 2048 | Author: sharbel | Hits:

[VHDL-FPGA-Verilog] ram

Description: 用VHDL描述了RAM的读写,很好的一个小东东,要你好好学习,用于开发RAM-OK,OK,VHDL ,FPGA,RAM,WRITE AND READ ,YOU WILL LIKE IT,ARE YOU?
Platform: | Size: 168960 | Author: greetree | Hits:

[VHDL-FPGA-Verilog] 256fft

Description:
Platform: | Size: 209920 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] BoXingFaSheng

Description: 多功能波形发生器VHDL程序与仿真 功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 --说明： SSS（前三位）和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号（ss）完成的（AMP的调节范围是0~5V，调节量阶为1/51V）。 --其中方波的幅度还可通过u0、d0调节输出数据的归一化幅值（AMP0）进行进一步 --细调（调节量阶为1/（51*255）V）。方波A的占空比通过zu、zp按键调节（调节 --量阶1/64*T）。系统采用内部存储器——RAM实现任意输入波形的存储，程序只支 --持键盘式波形特征参数置入存储，posting 为进入任意波置入(set)、清除（clr）状态 --控制信号，SSS控制存储波形的输出。P180为预留端口 -Wave Generator
Platform: | Size: 10240 | Author: 梁辰 | Hits:

[VHDL-FPGA-Verilog] ram

Description: vhdl program for random access memory and sequence detector
Platform: | Size: 1024 | Author: swap | Hits:

[VHDL-FPGA-Verilog] vlsiram

Description: VHDL RAM 16 * 8 source code FPGA
Platform: | Size: 1024 | Author: kirtikumar | Hits:

[VHDL-FPGA-Verilog] ssram

Description: 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
Platform: | Size: 1024 | Author: koo | Hits:

[VHDL-FPGA-Verilog] Ram-block-code

Description: It is a VHDL code for Block RAM
Platform: | Size: 1024 | Author: Umair | Hits:

[VHDL-FPGA-Verilog] dualportram_asch

Description: This an asychronous dual port ram-This is an asychronous dual port ram
Platform: | Size: 1024 | Author: iman | Hits:

[VHDL-FPGA-Verilog] ram_tb

Description: ram vhdl module for modelsim and vhdl design
Platform: | Size: 1024 | Author: majid | Hits:

[VHDL-FPGA-Verilog] RAM

Description: ram code in VHDL with its test code
Platform: | Size: 110592 | Author: sab | Hits:

[VHDL-FPGA-Verilog] shishi

Description: 基于FPGA的实时采样系统设计！双口ram典型应用！-FPGA-based real-time sampling system!
Platform: | Size: 1653760 | Author: 陈燕凯 | Hits:

[VHDL-FPGA-Verilog] ram

Description: hi this is ram code in vhdl
Platform: | Size: 8192 | Author: mani | Hits:

[VHDL-FPGA-Verilog] doc

Description: BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this project, the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. In this project, it has been demonstrated that accumulator based compaction scheme
Platform: | Size: 243712 | Author: sreekanth p | Hits:

[VHDL-FPGA-Verilog] 6soft_247MHz_channel

Description: lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟 input_buffer.vhd 输入控制 ri_addr_gen.vhd ri信息提取 ul_common_pack.vhd 变量定义 write_ram.vhd 解交织 deintlv_data.txt 数据源 deintlv_data_ack.txt ack信息源 deintlv_data_cqi.txt cqi信息源 deintlv_data_ri.txt ri信息源 sim_lib.tcl altera库编译 ue.tcl modelsim 脚本-upstream channel deinterleaving lte demultiplexing: RTL: ack_addr_gen.vhd ack address generation data_addr_gen.vhd data address generation control unit de_interl_mux_con_top.vhd de_interl_mux_con_ctrl.vhd top de_interl_mux_con_tt.vhd test platform de_mux_ram.vhd ram deinterl_pack.vhd delay variable definition delay.vhd delayb.vhd delay input_buffer.vhd input control information extraction ul_common_pack.vhd ri_addr_gen.vhd ri definition of a variable data source write_ram.vhd deinterleaving deintlv_data.txt deintlv_data_cqi.txt cqi deintlv_data_ack.txt ack information source information sources sources of information deintlv_data_ri.txt ri sim_lib. tcl altera library compile script ue.tcl modelsim
Platform: | Size: 200704 | Author: renliang | Hits:

[VHDL-FPGA-Verilog] 3Channel_CIS_Processor_with-VHDL.ZIP

Description: This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting -This is usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting
Platform: | Size: 15360 | Author: jeong | Hits:
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